Method for forming group iii/v conformal layers on silicon substrates

ABSTRACT

A method for forming a conformal group III/V layer on a silicon substrate and the resulting substrate with the group III/V layers formed thereon. The method includes removing the native oxide from the substrate, positioning a substrate within a processing chamber, heating the substrate to a first temperature, cooling the substrate to a second temperature, flowing a group III precursor into the processing chamber, maintaining the second temperature while flowing a group III precursor and a group V precursor into the processing chamber until a conformal layer is formed, heating the processing chamber to an annealing temperature, while stopping the flow of the group III precursor, and cooling the processing chamber to the second temperature. Deposition of the III/V layer may be made selective through the use of halide gas etching which preferentially etches dielectric regions.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims benefit of U.S. Nonprovisional patentapplication Ser. No. 13/436,644 (APPM/17117US), filed Mar. 30, 2012, andissued as U.S. Pat. No. 8,603,898, which is herein incorporated byreference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Embodiments of the invention generally relate to processes for forminggroup III/V materials on a silicon substrate using a group IIInucleation layer.

2. Description of the Related Art

Group III/V semiconductors have significant potential as usefulmaterials in high-temperature, high frequency and high powermicroelectronics and ultra-violet/blue/green optoelectronics by virtueof their wide bandgaps, high thermal conductivities and large electricalbreakdown fields. Microelectronic device applications include AlGaNGaNmultilayer-based laser diodes, high electron mobility transistors(HEMTs), field effect transistors (FETs), heterojunction bipolartransistors (HBTs), light emitting diodes (LEDs) and ultra-violetphotodetectors, as well as (Al,In,Ga) N-based devices generally,including devices for high-frequency, high-power communications, forhigh-density optical storage, full-color displays, and for other widebandgap semiconductor applications.

Further, surface layers capable of achieving the performance advantagesof group III/V materials may host a variety of high performanceelectronic devices such as CMOS and quantum well (QW) transistorsfabricated from extreme high mobility materials such as, but not limitedto, indium antimonide (InSb) and indium arsenide (InAs). Optical devicessuch as lasers, detectors and photovoltaics may also fabricated fromvarious other direct band gap materials, such as, but not limited to,gallium arsenide (GaAs) and indium gallium arsenide (InGaAs).

Despite the advantages and utility of such layers, the growth of groupIII/V materials on silicon substrates presents many challenges. Crystaldefects can be generated by lattice mismatch, polar-on-nonpolar mismatchand thermal mismatch between the group III/V semiconductor epitaxiallayer and the silicon semiconductor substrate. When the lattice mismatchbetween the epitaxial layer and substrate exceeds a few percent, thestrain induced by the mismatch becomes too great and defects aregenerated in the epitaxial layer when the epitaxial film relaxes.

Once the film thickness is greater than the critical thickness (film isstrained below this thickness and relaxed above this thickness), thestrain is relaxed by creating misfit dislocations at the film andsubstrate interface as well as in the epitaxial film. The epitaxialcrystal defects are typically in the form of threading dislocations,stacking faults and twins (periodicity breaks where one portion of thelattice is a mirror image of another). Many defects, particularlythreading dislocations, tend to propagate into the “device layer” wherethe semiconductor device is fabricated. Generally, the severity ofdefect generation correlates to the amount of lattice mismatch betweenthe group III/V semiconductor and the silicon substrate.

Various buffer layers have been used in attempts to relieve the straininduced by the lattice mismatch between the silicon substrate and thegroup III/V device layer and thereby reduce the detrimental defectdensity of the III/V layer. However, layer uniformity between differentsurface orientations of the silicon substrate has remained a constantproblem.

A related difficulty to depositing group III/V layers for CMOS featuresis conformal deposition on silicon substrates. Traditionally, inheteroepitaxy, buffer layers must be grown to be very thick, such as abuffer layer which is 1 or more microns thick, to overcome the mismatchbetween the layers and create a high quality crystalline film.

As such, the formation of a conformal layer on different crystalorientations requires the deposition of a thick layer to accommodate forabove crystal defects which is not optimal for small feature formationin CMOS.

Therefore, there is a general need for a deposition process with a highdeposition rate that can deposit group III/V films uniformly over alarge substrate or multiple substrates without regard for latticemismatch, polar-on-nonpolar mismatch or other difficulties. Further,there is a need in the art for an improved deposition method which doesnot require a thick buffer layer for the growth of group III/Vcrystalline layers on a silicon substrate.

SUMMARY OF THE INVENTION

Embodiments of the invention generally relate to methods for forminggroup III/V layers using a group III nucleation layer. The group III/Vlayer can be any group III/V layer and can be deposited under normalconditions for metal organic chemical vapor deposition (MOCVD) known inthe literature. It is important that the deposition be conformal overvarious surface orientations while simultaneously producing a highquality crystalline film.

In one embodiment, a method for forming a conformal layer on a substrateis provided which can include positioning a substrate within aprocessing chamber after removing the native oxide from the substrate,heating the substrate to a first temperature, cooling the substrate to asecond temperature, and flowing a group III precursor into theprocessing chamber to seed the substrate.

One or more embodiments can further include maintaining the processingchamber at the second temperature while flowing a group III precursorand a group V precursor into the processing chamber until a conformalbinary III/V layer is formed. The processing chamber can then be heatedto a third temperature, while stopping the flow of the group IIIprecursor. Processing terminates after subsequent cooldown back to thesecond temperature.

In another embodiment, the method for forming a conformal layer on asubstrate can include positioning a substrate within a processingchamber, adjusting the temperature of the processing chamber to a firsttemperature, flowing a group III precursor into the processing chamberto create a nucleation layer, flowing a group III precursor and a groupV precursor into the processing chamber to create a binary III/V bufferlayer, heating the processing chamber to a second temperature, whilestopping the flow of the second group III precursor, cooling theprocessing chamber to the first temperature, sequentially repeating theprecursor, annealing and cooling steps until the desired binary III/Vbuffer layer thickness is reached.

In some embodiments, a silicon substrate can include an upper surfacewith both dielectric and semiconductor regions with a group IIInucleation layer disposed on at least one surface of the siliconsubstrate, wherein the group III nucleation layer is composed of one ormore group III elements, and a group III/V buffer layer on top of thegroup III nucleation layer.

In one or more embodiments, the substrate can further include one ormore binary or ternary group III/V layers formed on the buffer layer.The binary or ternary group III/V layers can include one or more groupIII and one or more group V elements, which can be composed of the samegroup III or the same group V element as used in either the buffer layeror the nucleation layer and can be a conformal layer.

BRIEF DESCRIPTION OF THE DRAWINGS

So that the manner in which the above recited features of the inventionare attained and can be understood in detail, a more particulardescription of the invention, briefly summarized above, may be had byreference to the embodiments thereof which are illustrated in theappended drawings.

FIG. 1A depicts a flow diagram of the method for forming a nucleationlayer and a buffer layer on a substrate, according to one or moreembodiments.

FIG. 1B depicts a flow diagram of the method for forming a binary orternary group III/V layer on a substrate with a nucleation layer andbuffer layer formed, according to one or more embodiments.

FIG. 2 depicts the substrate with group III/V layers formed thereon byone or more of the previously described methods.

It is to be noted, however, that the appended drawings illustrate onlyexemplary embodiments of this invention and are therefore not to beconsidered limiting of its scope, for the invention may admit to otherequally effective embodiments.

DETAILED DESCRIPTION

Embodiments of the invention generally relate to methods for forminggroup III/V materials on silicon surfaces and the resulting compositionforming a buffer layer on a nucleation layer composed of a group Illelement. In one embodiment, a method for forming a conformal layer on asubstrate is provided which can include removing the native oxide fromthe substrate, positioning a substrate within a processing chamber,heating the substrate to a first temperature, cooling the substrate to asecond temperature, and flowing a group III precursor into theprocessing chamber. The group III precursor can be selected from allknown group III precursors.

The first temperature, which can correspond to a post cleaning step, canrange from about 400° C. to about 800° C., with preferred embodimentsranging from about 400° C. to about 500° C. The post cleaning step canbe used to remove remaining contaminants from the surface of thesubstrate. The second temperature, which can correspond to a layerformation step, can range from about 250° C. to about 400° C., such asabout 290° C. to about 340° C., with a preferred embodiment of 300° C.In one or more embodiments, the group III precursor can be flowed intothe processing chamber for up to 15 seconds, such as a range of about 3to about 10 seconds, with preferred embodiments ranging from about 3 toabout 5 seconds.

One or more embodiments can include maintaining the processing chamberat the second temperature, flowing a group III precursor and a group Vprecursor into the processing chamber until a conformal layer between 5nm and 50 nm thick is formed, heating the processing chamber to a thirdtemperature, while stopping the flow of the group III precursor, andcooling the processing chamber to the second temperature. The method caninclude stopping the group V precursor flow to the processing chamberwhen the process is complete. The conformal III/V layer formed by theaddition of the group V precursor, after treatment with the group IIIprecursor, can be between 5 nm and 100 nm thick, more specificallybetween 5 nm and 50 nm and with preferred embodiments of between 10 nmand 30 nm. The third temperature, which can be an annealing temperature,can range from about 400° C. to about 600° C., with preferredembodiments from about 450° C. to about 550° C. The group V precursorcan be selected from all known group V precursors.

Group III and group V precursors used in binary or ternary III/V layersare chosen according to the specific electrical property desired. GroupIII precursors can include Trimethyl Indium, Trimethyl Gallium, TriethylGallium, Trimethyl Aluminum. Group V precursors can includeTertiarybutylarsine, Tertiarybutyl Phosphine, Triethyl Antimony, Arsine(AsH₃), and Phosphine (PH₃).

In one or more embodiments, the group III precursor used in any of thedescribed layers can be the same group III precursor group as any otherlayer. Further, the group III precursor can be flowed into theprocessing chamber as a continuous flow from the nucleation layer stepto the buffer layer formation.

One or more embodiments can also include the use of halide gases, suchas chlorine or hydrogen chloride, to control deposition of the groupIII/V layers. The halide gas can be used in either a thermal etchingprocess or a plasma assisted etching process to primarily etch thedielectric regions of substrate. As such, group III and group V elementscan be removed preferentially from the surface of the dielectricregions, allowing deposition to accumulate only on semiconductorregions.

In another embodiment, a method for forming a conformal layer can alsoinclude maintaining the processing chamber at the second temperature,flowing at least one group III precursor and at least one group Vprecursor, wherein three precursor gases are used, into the processingchamber until a conformal ternary group III/V layer is formed on a groupIII/V layer, heating the processing chamber to the third temperature,while stopping the flow of the group III precursor, cooling theprocessing chamber to the second temperature, and stopping the group Vprecursor flow to the processing chamber to terminate the process.

In another embodiment, a method for forming a conformal III/V layer on asubstrate can include positioning a substrate within a processingchamber, adjusting the temperature of the processing chamber to a secondtemperature, flowing a group III precursor into the processing chamber,maintaining the second temperature while flowing a group III precursorand a group V precursor into the processing chamber until a film isformed, heating the processing chamber to a third temperature, whilestopping the flow of the group III precursor, cooling the processingchamber to the second temperature, sequentially repeating the bufferprecursor, annealing and cooling steps until the desired buffer layerthickness is reached, wherein the sequence can be repeated one or moretimes, and stopping the group V precursor flow to the processingchamber.

In one or more embodiments, the incremental buffer layer created by thesequential repeat can be limited to no more than 50 nm of thickness perrepeat, such as the incremental buffer layer of up to 30 nm thick, witha preferred embodiment of the incremental buffer layer up to 20 nmthick.

In another embodiment, a silicon substrate can include an upper surfacewith both dielectric and semiconductor regions, a group III nucleationlayer disposed on at least one surface of the silicon substrate, whereinthe group III nucleation layer is composed of one or more group IIIelements, and a group III/V buffer layer on top of the group IIInucleation layer. The combined nucleation layer and the buffer layer canbe from 50 Å to 500 Å thick, such as from 50 Å to 400 Å thick withpreferred embodiments including from 100 Å to 300 Å thick.

In one embodiment, the thin conformal group III/V layer can include oneor more binary or ternary group III/V layers formed on the buffer layer.The binary or ternary group III/V layers can be in any order withrespect to each other. The one or more binary or ternary group III/Vlayers can be composed of the same group III or the same group V elementor compound as the buffer layer in any conceivable permutation of theabove combination. The group III element in the nucleation layer can bethe same as the group III element in the buffer layer or the binary orternary group III/V layer. The group III and group V elements used inany of the above layers can be of any type available in a group III orgroup V precursor.

The binary or ternary group III/V layers can cover the one or moresurfaces conformally and without regard to orientation of the silicon,such as a group III/V layer that is conformal over the (100) and (110)orientation of a silicon substrate. Examples of binary layers caninclude Gallium phosphide (GaP), Indium phosphide (InP), or IndiumArsenide (InAs). Examples of ternary layers can include Indium GalliumArsenide (InGaAs) or Aluminum Indium Arsenide (AllnAs).

FIG. 1A depicts a flow diagram of a method 100 for forming a nucleationlayer and a buffer layer on a substrate, according to one or moreembodiments.

Before positioning the substrate, the method 100 can include removingthe native oxides from the substrate, as in step 102. The procedure forattempting to remove any surface oxide can include various wet etches,generally concluding with a dip in dilute Hydrofluoric Acid (HF).Removal of surface oxides can also include using a dry etching process,such as plasma or thermal methods employing NH₃ diluted with H₂.

The method 100 can include positioning the substrate in a processingchamber, as in step 104. The processing chamber can be of any typecommonly used for MOCVD processes. Though the invention described herefocuses on MOCVD processes, it is envisioned that other processes knownin the art for deposition of the III/V layer, such as vapor phaseepitaxy (VPE) or molecular beam epitaxy (MBE) methods, may be used.

Within the processing chamber, the substrate can be heated at a firsttemperature, as in step 106, at which point the residual contaminantsare removed from the substrate. The chamber can be heated from about400° C. to about 900° C., with preferred embodiments ranging from about550° C. to about 650° C.

The pre-treatment of the substrate can include lowering the chambertemperature to a second temperature, as in step 108. At the lowertemperature, which can range from about 250° C. to about 400° C., suchas about 290° C. to about 340° C., with a preferred embodiment of 300°C., the nucleation layer can deposit on the exposed surface of thesubstrate.

The method can include pretreatment of the substrate with a group IIIprecursor for a short period of time at the second temperature, as instep 110. This will deposit a thin conformal nucleation layer of thegroup III precursor on the exposed surfaces of the substrate. The shortperiod of time should be no more than 15 seconds, such as a range of3-10 seconds, with preferred embodiments of 3-5 seconds.

After deposition of the nucleation layer, the method can include flowinga group III precursor and a group V precursor into the chamber to grow abinary group III/V buffer layer, as in step 112. The buffer layer can begrown from up to 50 nm thick, in one or more embodiment from 5 to 40 nmthick, and in some preferred embodiments the buffer layer can be fromabout 10 to 30 nm thick. The buffer layer can be composed of a binary orternary III/V film, with preferable embodiments employing a binary III/Vfilm.

After the buffer layer has deposited on the nucleation layer, the methodcan include raising the temperature to a third temperature whilestopping the group III precursor flow, as in step 114. The thirdtemperature can be a temperature which can properly anneal the layer onthe substrate to make it very crystalline. The third temperature canrange from about 400° C. to about 600° C., with preferred embodiments offrom about 450° C. to about 550° C. The chamber should be increased tothe third temperature within 15 seconds of finishing growth of thebuffer layer to assure proper annealing and formation of the crystallinestructure.

Not wishing to be bound by theory, it is believed that the group IIIprecursor has a better sticking coefficient which allows the group IIIprecursor to bind more effectively to the silicon substrate whilesimultaneously creating a binding site for the group V precursor. Thegroup V precursor will not create a nucleation layer which can serve asa surface for III/V layer growth. Therefore, the group V precursor flowis continued after stopping the group III precursor flow to saturate thebinding sites left by the group III precursor on the substrate withoutthe expectation of continued layer growth.

Once the binary III/V layer has been annealed, the chamber can be cooledto the second temperature, as in step 116. The group V precursor can bestopped simultaneously with the cooling of the chamber, if the processis to be terminated. Otherwise, after this step 116, one or more binaryor ternary group III/V layers can be formed on the buffer layer.

It is important to note that when creating the buffer layer, it ispreferential to form a binary III/V layer on the surface of thenucleation layer. The formation of a ternary III/V layer as the bufferlayer can be less stable for subsequent layer growth.

It is not necessary that further layers be formed on the substrate. Theannealed layer can be the deposited III/V layer used in subsequentprocesses.

FIG. 1B depicts a flow diagram of the method for forming a binary orternary group III/V layer on a substrate with a nucleation layer andbuffer layer formed, according to one or more embodiments.

Once the buffer layer has been completed, the method can includemaintaining the processing chamber at the second temperature, as in step118. At this point, the binary and ternary III/V layers can be layeredin any order. Further, there is no required composition for the binaryor ternary III/V layers. They can contain the same or different groupIII or group V elements from the previous layers.

At the second temperature, the method can include flowing a group IIIprecursor and a group V precursor into the processing chamber, as instep 120. The precursors can be mixed in this or subsequent layers withno detrimental effect on quality. The flow of the precursors should becontinued until a desired III/V layer thickness is achieved.

Once the binary or ternary III/V layer has been deposited, the methodcan include heating the chamber to a third temperature while stoppingthe flow of the group III precursor, as in step 122. As above, the spikein temperature helps form a more crystalline structure in the III/Vlayer. Preferably, the heat spike should be done within 15 seconds ofstopping the flow of the group III precursor, though it is possible towait longer.

After the heat spike, the processing chamber can be cooled to the secondtemperature, as in step 124.

Once the chamber has cooled, the flow of the group V precursor to theprocessing chamber can be stopped, as in step 126, to terminate theprocess.

Though this embodiment includes a more detailed description of thebinary and ternary III/V layer deposition process, it is contemplatedthat the binary and ternary III/V layers may be deposited by any methodthat can be used to deposit a group III/V layer. Techniques fordepositing group III/V layers include MOCVD, VPE and MBE.

FIG. 2 depicts the substrate with group III/V layers formed thereon byone or more of the previously described methods.

The silicon substrate 300 can have one or more exposed surfaces, such as302 a and 302 b. The exposed surfaces can be of a different surfaceorientation, such as silicon with (100) or (110) orientation. Though theexamples list only two surface orientations, the embodiments describedhere are not to be considered limited to only those orientations.

The silicon substrate 300 can have a nucleation layer 304 deposited onthe one or more exposed surfaces 302. The nucleation layer 304 can beless than or equal to 50 Å, such as 10 Å. Further, the nucleation layercan be primarily composed of one or more group III elements, such asaluminum (Al), gallium (Ga), or indium (In).

A buffer layer 306 can be disposed over the exposed portions of thenucleation layer 304. The buffer layer 306 can be a binary III/V layerand can be substantially crystalline. Further, the buffer layer 306 canbe conformally deposited over the nucleation layer 304. The buffer layercan be between up to 50 nm thick, such as between 5 and 40 nm thick,with preferred embodiments of between 10 nm and 30 nm thick.

A group III/V layer 308 can be disposed over the exposed portions of thebuffer layer 306. The group III/V layer 308 can be either a binary orternary III/V layer and can be conformally deposited over the exposedsurface of the buffer layer 306.

Though this embodiment shows only one group III/V layer 308, otherembodiments may have one or more group III/V layers, which may be in anyorder with regards to binary or ternary layers and may be of anythickness within the range of thicknesses available for group III/Vlayers.

Thus, methods for the deposition of a conformal group III/V layer over asilicon substrate having a group III nucleation layer are provided. Thenovel method of epitaxially growing a group III/V layer has numerousadvantages over the prior art including formation on any surfaceorientation, much thinner layers, faster throughput and higher qualitycrystalline structures. This is beneficial for the production of anyfeature that requires the deposition of group III/V layers, such as CMOSproduction. Exposed regions of silicon can be covered by the conformalgroup III layer which allows for the deposition of conformal subsequentgroup III/V layers.

While the foregoing is directed to embodiments of the present invention,other and further embodiments of the invention may be devised withoutdeparting from the basic scope thereof, and the scope thereof isdetermined by the claims that follow.

1-20. (canceled)
 21. A method of forming a layer, comprising:positioning a substrate in a processing chamber, the substratecomprising an exposed surface; delivering a first group III precursor tothe exposed surface of the substrate while depositing a nucleation layeron the exposed surface; and delivering a second group III precursor anda group V precursor while depositing a group III/V layer.
 22. The methodof claim 21, wherein the group V precursor continues to flow after theflow of the second group III precursor is stopped.
 23. The method ofclaim 21, wherein the chamber is heated to from about 550° C. to about650° C. prior to delivering the first group III precursor.
 24. Themethod of claim 23, wherein the chamber is cooled to about 250° C. toabout 400° C. prior to stopping the group V precursor flow.
 25. Themethod of claim 21, wherein the first group III precursor and the secondgroup III precursor are aluminum, gallium, indium or combinationsthereof.
 26. The method of claim 21, wherein the group III/V layer is aternary layer.
 27. The method of claim 21, wherein the group III/V layeris less than 50 nm thick.
 28. A method of forming a layer, comprising:cleaning an exposed surface of a substrate; depositing a group IIInucleation layer over the exposed surface at a first temperature;depositing a binary or ternary group III/V layer on the group IIInucleation layer at a second temperature; and annealing the binary orternary group III/V layer.
 29. The method of claim 28, wherein the groupIII nucleation layer is deposited to a thickness of between 10 nm and 30nm.
 30. The method of claim 28, wherein the second temperature is higherthan the first temperature.
 31. The method of claim 28, furthercomprising depositing one or more additional binary or ternary groupIII/V layers and annealing the additional binary or ternary group III/Vlayers.
 32. The method of claim 31, wherein at least one of theadditional binary or ternary group III/V layers comprises a group IIIelement or a group V element which is different from the previous binaryor ternary group III/V layer.
 33. The method of claim 32, wherein thesecond temperature is maintained during the deposition of the additionalbinary or ternary group III/V layers.
 34. The method of claim 28,wherein the binary or ternary group III/V layer is annealed at atemperature between about 400° C. and about 600° C.
 35. A device,comprising: a silicon substrate comprising: a first surface; and asecond surface disposed opposite the first surface; a group IIInucleation layer disposed on the first surface of the silicon substrate;and a group III/V buffer layer on top of the group III nucleation layer.36. The device of claim 35, further comprising one or more binary orternary group III/V layers formed on the group III/V buffer layer. 37.The device of claim 36, wherein the group III/V buffer layer or the oneor more binary or ternary group III/V layers are composed of the samegroup III or the same group V element as the buffer layer.
 38. Thedevice of claim 35, wherein the group III nucleation layer and groupIII/V buffer layer comprise aluminum, gallium, indium or combinationsthereof.
 39. The device of claim 35, wherein the group III/V bufferlayer comprises phosphorus, arsenic or combinations thereof.
 40. Thedevice of claim 35, wherein the group III/V buffer layer is a binarylayer.